Inductance in PCB Layout: The Good, the Bad, and the Fugly

Inductance in PCB Layout: The Good, the Bad, and the Fugly

When current flows through a conductor it becomes an inductor, when there is an inductor there is an electromagnetic field (EM). This can cause a variety of issues during PCB layout if you don’t plan properly, and sometimes we get burned even when we think we have planned for unwanted inductance and the effects that come with them.

When doing high speed logic we need to be able to deliver sudden changes in current to the devices if we want to have proper switching times and logic levels. Unfortunately inductance is usually not a friend in these circumstances as it resists those sudden changes in current. If the high speed devices are driving capacitive loads, which themselves are resisting changes in voltage, even more instantaneous current is needed.

Simply put, inductors resist a change of current, and can act as a low pass filter when in series with the signal or power supply flow. Inductors do this by storing energy in the flux surrounding the conductor. Alternatively capacitors resist a change in voltage (again by storing energy) and can act as a high pass filter when in series with the signal. This makes them a valuable tool in the fight against unwanted inductance in power supply distribution.

In the video below, and the remainder of this article, I’m going to dive into the concept of inductance and how it affects our design choices when laying out circuit boards.

It may be something you’ve never considered before, but the electrical properties of PCB traces matter a lot as electronic components continue to increase in speed. Resistance in the traces results in voltage drop and also slows the charging of capacitive loads. Inductive Reactance (XL), which can be thought of as a frequency dependent resistance when it comes to supplying current, further complicates our design challenges. But having a basic understanding of what we’re up against will help you recognize problems while designing, instead of after assembling your prototype boards.


The math and practices of high speed design.
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Here you can see three of my favorite books which are a great resource if you want to take a deep dive into these topics. In the video I walk through several topics from these texts, beginning with DC resistance in traces which ultimately result in the table below. You can see here that an inch of an average PCB trace can have between 0.1Ω and 15Ω of impedance depending on frequency or risetime of the signal. If we plug the impedance into Ohms law, we see that 10Ω at 0.1A is a 1V drop in voltage.

Frequency (MHz) Rise Time (ns) Impedance (Ω)
1 318 0.1
10 31.8 1.0
30 10.6 2.8
50 6.4 4.7
70 4.5 6.6
90 3.5 8.5
110 2.9 10.4
160 2.0 15.0
Impedance of a One Inch Long Printed Circuit Board Trace (15 nH Inductance). Recreated from Noise Reduction Techniques by Henry Ott

Knowing that voltage drops in circuit board traces are usually unwanted,  we can conclude that inductance in those sames traces is also therefore unwanted. Consequently the more inductance there is, the worse the effect it has on our circuit.

What may not be intuitive to all is that the larger of a loop of conductor, the larger the Inductance. In other words, the larger the area inside the loop formed by the power and ground return paths, the higher the inductance, the higher the resistance to high speed demands for current.

After years of knowing this relationship, but not knowing the specific formula for calculating, I found this formula in the book High Speed Digital Design:

L approx 5Y lnbegin{bmatrix} X\ -\ W end{bmatrix}

The formula shows inductance as a function of area using the variables as follows:

  • L = Inductance
  • X,Y = Dimension
  • W = Width of conductor

Simply put, power and ground return paths should be as close together as possible. This minimizes inductance and limits the consequential voltage drop and helps to preserve fast changes in current in response to demand.

Knowing this you can see just how bad a common practice used on some prototyping boards, known as “interdigitated” , really is. You will often see a voltage bus on one side of a protoboard and a ground bus on the other (as is shown below). In effect the power supply loop area is close to the size of the entire board. Increasing the width of the conductor doesn’t really lower the overall inductance much due to its place in the equation. The best answer is to reduce the size of the area by techniques such as creating a grid of the power and ground paths or through judicious use of ground and power planes.

Interdigitated power distribution results in a larger area and higher inductance
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Apertures in ground plane can increase current path area and increase inductance.
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Using a ground plane doesn’t automatically mean that the inductance problem is minimized; care must be taken to not inadvertently create problems by placing obstacles on the ground or power layers. As the frequency of the signal goes up, the closer the return path will follow it on the ground (or power) plane. If the signal goes through a gap in the plane, such as might be created by a connector or routing a signal trace on a plane layer, the return path may have to take a detour, which increases the loop, sometimes unexpectedly.

An example of how the return path can be affected by a hole in the ground plane is shown. In practice the ground or power plane is often buried, making this issue may not be readily visible. Cross talk can also become an issue if two singles end up squeezing through the same small area between two obstacles.